STLC1502 View Datasheet(PDF) - STMicroelectronics
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MFG CO.
'STLC1502' PDF : 81 Pages View PDF
STLC1502
With this approach every Descriptor will have the DMA_Next field pointing to the next Descriptor in the
chain (the last one will point to the first one), the NXT_EN bit, the VALID bit and the NPOL_EN bit on.
The DMA_MAC will keep fetching the Descriptors one by one until it finds one with its VALID bit set to off.
Every time the DMA_MAC completes a Descriptor (frame) it saves the transfer status into TxRx_Status,
it turns its VALID bit to off and raises the TX_CURR_DONE interrupt bit.
6.5.8 Frames reception (RX)
The frame reception process is something that needs to be activated at the beginning and kept always
running. For this reason the closed Descriptor list (see above) is much more useful than the open list
approach.
Again, with this approach every Descriptor will have the DMA_Next field pointing to the next Descriptor in
the chain (the last one will point to the first one), the NXT_EN bit, the VALID bit and the NPOL_EN bit on.
The CPU starts the transfer activity loading the DMA Next register of the DMA_MAC with the physical
location of the first Descriptor and set the DMA Start register enable bit to on.The DMA_MAC will start
fetching the Descriptors one by one, driven by the frames reception from the line. Every time the
DMA_MAC completes a Descriptor (frame) it saves the transfer status into TxRx_Status, it turns its
VALID bit to off and raises the TX_CURR_DONE interrupt bit.
Eventually, the DMA_MAC will be faster than the CPU, it will wrap around the Descriptor chain and find a
Descriptor still invalid.
Then the DMA_CNT keeps polling the invalid descriptor, raising each time the TX_NEXT interrupt bit (if
enabled), until some Descriptor gets available (note that in this case some frame could be lost). In the
meantime the CPU should consume the frames received and set the VALID bit to on of all the Descriptor
released.
As soon as the DMA_CNT finds the Descriptor valid again, it will be able to complete the transfer and to
fetch the next Descriptor.
6.5.9 Ethernet block Register Map [0x0C680000]
The base address of the Ethernet registers is 0x0C680000
The memory map of the Dual MAC Ethernet block is shown below:
Address
Register Name
DMA_MAC1 Eth_base1=0x0C680000
Eth_base1+ 0x0000 DMA_ST&CNTL
Eth_base1+0004
DMA_INT_EN
Eth_base1+0008
DMA_INT_STAT
Eth_base1+000C
Eth_base1+ 0x0010 RX_DMA_START
Notes
DMA Status and Control Register
DMA Interrupt Sources Enable Register
DMA Interrupt Status Register
Reserved
RX DMA start Register
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