STLC1502 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STLC1502

VOICE OVER IP PROCESSOR

STMicroelectronics 

Prev 31 32 33 34 35 36 37 38 39 40 Next

INTERRUPT_MASK

IRQRawStatus

STLC1502

Enable

IRQStatus

Interrupt Source

Interrupt Pending

Other Interrupt Bit Slices

Figure 12: IRQ control block

7.4.3 Interrupt register map [0x0C100000]

The base address of the timer register is 0x0C100000

The offset of any particular register from the base address is the following.

nIRQ

Address

Int.Base + 0x00

Register Name

IRQStatus

Int Base+ 0x04 IRQRawStatus

Int.Base + 0x08 IRQEnableSet

R/W Notes

R

For every IRQ interrupt cause,

a ‘1’ means an active pending

interrupt that has to be served

by the ARM

R

For every IRQ interrupt source,

a ‘1’ means an active pending

interrupt “before” the mask (w/

o considering the mask)

R/W For every IRQ interrupt source,

a ‘0’ means that even if an

interrupt source is active, it has

to be stopped (masked). The

write operation of 1 to a given

bit, enable the corresponding

interrupt

39/81

Share Link: