STLC1502 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC1502' PDF : 81 Pages View PDF
STLC1502
Table : Register map of the DPORT peripheral
Register Name
Output Status reg
ARM 7 Address
HPI_regBase +0x0C00
Host Processor addr.
0x0
Output Index reg
HPI_regBase +0x0C02 0x1
Output Mask reg
Input Status reg
HPI_regBase +0x0C04 0x2
HPI_regBase +0x0C06 0x3
Input Index reg
HPI_regBase +0x0C08 0x4
Input Mask reg.
HPI_regBase +0x0C0A 0x5
Output Message buffer
HPI_regBase +0x0000
-
0x6
HPI_regBase +0x01FE
Output Message buffer
HPI_regBase +0x0200
-
0x7
HPI_regBase +0x03FE
7.10 Dual Port SRAM
A dual port SRAM 4096x16 connected between the APB bus and the X bus of the D950 domain, is used as a
mailbox between the ARM7 and the D950. The DPRAM can be written/read everywhere by both the ARM and
the D950. The DPRAM bank has two status sections consisting of 32, 16 bits memory locations, and a message
section consisting 4064 16 bit memory locations.
There are 4 hardware registers: ARM and D950 mailbox mask registers and ARM and D950 mailbox registers.
• Mailbox registers: the writing of any value in a STATUS location will set the corresponding bit in the
MAILBOX to 1. This will generate an interrupt if the corresponding mailbox MASK register bit is set to
1, and won’t if the bit is set to 0. Reading a STATUS location will clear the corresponding bit in the
MAILBOX to 0. (note: Only the ARM can clear the D950 mailbox on a read, and only the D950 can
clear the ARM mailbox on a read. Likewise only the ARM can set the ARM Mailbox bits by writing to
the ARM STATUS registers, and only the D950 can set the D950 Mailbox by writing to the D950 STA-
TUS registers).
• Mailbox MASK registers: writing 0 in a bit location will allow the STATUS location to set the corre-
sponding bit in the MAILBOX, but will mask out the generation of an interrupt. The Mailbox MASK
registers are both reset to all 0’s, so, by default, no interrupts will be generated.
7.10.1 DPRAM protocol
There can be up to 16 different communication channels that the D950 and the ARM can use to exchange mes-
sages between them. The allocation of the 4064 addressable message buffers locations in the DPRAM is com-
pletely under the programmer’s control. There is no intervention by the hardware on the DPRAM other than use
the first 32 locations to set and clear the MAILBOX registers and ultimately generate interrupts. A software pro-
tocol must be established in advance to safely pass messages.
Every time one of the two devices wants to write or receive a message, it should follow the example protocol
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