STLC1511 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC1511' PDF : 31 Pages View PDF
STLC1511
Table 11. Detailed Register Map: AFE Control 3
Title:
AFE Control 3 (Power Down Reg)
Label:
Power Down
Access Type:
Address:
010
Bits Used:
Description:
Power Down Register
Bit Label
Bit(s)
Value
Bit Description
Rx Opamp Power
b3
0
Down
1
Power up RxPGA
Power down RxPGA
not used
b7-b4
<1>During power down the Tx serial interface is also disabled and TXSCLK is tristated.
<2>During power down the Rx serial interface is also disabled and RXSCLK and RXSOUT[1:0] are tristated
R/W
3
Reset
1
0
Table 12. Detailed Register Map: AFE Control 4
Title:
Label:
Address:
Description:
Bit Label
Clip Indicator Enable
Tx Loop back
PLL Phase/Freq Input
Select (Test Mode)
DIV Output
(Test Mode only)
not used
AFE Control 4 (Misc. Control)
Misc Control
Access Type:
011
Bits Used:
Mode Control/Misc.
Bit(s)
Value
Bit Description
b0
0
1
Clip indicator disabled
Clip indicator enabled
b1
0
1
Normal operation
Test mode. Tx data sent to serial I/F is
muxed to Rx input and trasmitted via the
serial I/F
b2
0
1
Source of PLL phase-frequency detector
feedback input.
Output of feedback dividers.
Signal on FREF is sent directly to PFD (ref
input) and signal on pin CK35M is sent
directly to PFD (vco input).
b3-b4
00
01
10
11
normal operation
Output of DIV69 counter is output to
DIGREF pin
Output of DIV2/3/4/8 counter is output to
DIGREF pin
Output of DIV5 counter is output to
DIGREF pin
b7-b5
R/W
5
Reset
1
0
0
0
000
23/31
Share Link: 
