STLC1511 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC1511' PDF : 31 Pages View PDF
STLC1511
Table 13. Detailed Register Map: AFE Control 5
Title:
AFE Control 5 (PLL Control)
Label:
PLL Control
Access Type:
R/W
Address:
100
Bits Used:
7
Description:
PLL Control Register
Bit Label
Bit(s)
Value
Bit Description
Reset
Clock Source Control b0-b1
00
(CO External Clock Mode.) Output of
00
clock selection MUX is from FREF pin.
This state also powers down the PLL and
oscillator driver.
(CO Oscillator Mode.) Output of clock
01
selection MUX is from output of divide by
5.
(CPE Mode). Output of clock selection
10
MUX is from output of oscillator driver.
(Other CPE Mode). Output of clock
selection MUX is from output of oscillator
11
driver.
OSC Mode1
b2
0
1
(CO Oscillator mode.) AFE is configured 1
to drive external 88.32MHz LC oscillator.
(CPE mode.) AFE is configured to drive
external 35.328MHz crystal oscillator.
PLL Mode
b3
0
1
PLL active (PFD,CP active)
0
PLL Inactive (PFD,CP powered down)
FREF Mode2
b5-b4
00
FREF frequency is 2.56MHz
00
01
FREF frequency is 1.536MHz
10
FREF frequency is 2.048MHz
11
FREF frequency is 4.096MHz
DIGREF Enable
b6
0
DIGREF Output pin tristated
1
1
DIGREF Output pin active
reserved
b7
0
<1>Presently there is no difference in the oscillator driver between CO Oscillator and CPE modes so this bit is unused. However, it
may be required in the future and should be programmed correctly in case needed.
<2>For FREF at 2.56MHz (b5:b4 = “00”), the compare frequency for the PLL is at 1.28MHz. For all other FREF modes the compare
frequency is at 512kHz.
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