STLC2411 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC2411' PDF : 25 Pages View PDF
STLC2411
interface is programmable to be CVSD, A-Law or µ-Law.
The PCM block is able to manage the PCM bus with up to 3 timeslots.
PCM clock and data are in master mode available at 2 MHz or at 2.048 MHz to allow interfacing of stan-
dard codecs.
The four signals of the PCM interface are:
– PCM_CLK :
– PCM_SYNC :
– PCM_A :
PCM clock
PCM 8kHz sync
PCM data
– PCM_B :
PCM data
Directions of PCM_A and PCM_B are software configurable.
Three additional PCM_SYNC signals can be provided via the GPIOs. See section 12 for more details.
Figure 9. PCM (A-law, µ-law) standard mode
PCM_CLK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
PCM_SYNC
PCM_A
PCM_B
B
B
125µs
B
B
D02TL558
Figure 10. Linear mode
PCM_CLK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
PCM_SYNC
PCM_A
PCM_B
125µs
D02TL559
Table 13. PCM interface timing.
Symbol
Description
PCM Interface
Fpcm_clk Frequency of PCM_CLK (master)
Fpcm_sync Frequency of PCM_SYNC
tWCH High period of PCM_CLK
tWCL Low period of PCM_CLK
tWSH High period of PCM_SYNC
tSSC Setup time, PCM_SYNC high to PCM_CLK low
tSDC Setup time, PCM_A/B input valid to PCM_CLK low
tHCD Hold time, PCM_CLK low to PCM_A/B input invalid
tDCD Delay time, PCM_CLK high to PCM_A/B output valid
Min
Typ
Max Unit
2048
kHz
8
kHz
200
ns
200
ns
200
ns
100
ns
100
ns
100
ns
150
ns
20/25
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