Pinout
STLC2500A
The column Reset and Default show the state of the pins in reset and the default value after
reset. For the output pin the default drive capability is 2 mA.
Table 12. STLC2500A pin list (functional and supply)
Name
Pin #
Description
DIR
Reset
Default
after
reset
VDD_
IO_x
Clock and reset pins
RESETN
K03 Global reset - active low
RF_CLK_IN H10 Reference clock input
LP_CLK
K05 Low power clock input
I
Input Input
A
I
Input Input
(1)
I
Input Input
B
SW initiated low power mode
HOST_
WAKEUP
BT_WAKEUP
J05
Wake-up signal to host
(Open drain output)
J03 Wake-up signal to Bluetooth
I/O
Input PD
Output
high
A
I
Input(2) Input
A
UART interface
UART_RXD J07 UART receive data
I
Input PD Input
A
UART_TXD
K07 UART transmit data
O/t (I/O)
Tri-state
PD
Output
high
A
UART_CTS
J06 UART clear to send
I
Input PU
(2)
Input
A
UART_RTS
K06 UART Request to send
O/t (I/O)
Tri-state
PU
Output
low
A
PCM interface
PCM_SYNC E02 PCM frame signal
PCM_CLK
E01 PCM clock signal
PCM_A
F02 PCM data
PCM_B
F01 PCM data
JTAG interface
JTAG_TDI
C01 JTAG data input
JTAG_TDO
B01 JTAG data output
JTAG_TMS
D01 JTAG mode signal
JTAG_NTRST C02 JTAG reset active low
JTAG_TCK
D02 JTAG clock input
I/O Input PD Input PD A
I/O Input PD Input PD A
I/O Input PD Input PD A
I/O Input PD Input PD A
I
Input PU Input PU A
O/t Tri-state Tri-state
A
I
Input PU Input PU A
I
Input PD Input PD A
I
Input(3) Input
A
General purpose Input/Output pins
GPIO_0
GPIO_1
GPIO_2
GPIO_3
J08 General purpose IO
K08 General purpose IO
J09 General purpose IO
K09 General purpose IO
I/O Input PD Input PD A
I/O Input PD Input PD A
I/O Input PD Input PD A
I/O Input PD Input PD A
12/37