STLC2500A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC2500A' PDF : 37 Pages View PDF
STLC2500A
Pinout
Table 13. STLC2500A pin list (test)
Name
Pin #
Analogue test pin
Description
DIR
Reset Default VDDIO
VDD_T
ABUS_IN_QN
ABUS_QP_IP
ABUS_IP_QP
ABUS_QN_IN
C06 Test supply
A08 Test pin
A09 Test pin
B07 Test pin
B08 Test pin
I/O
Input(1) Input (1)
I/O
Input (1) Input (1)
I/O
Input (1) Input (1)
I/O
Input (1) Input (1)
ANA_1
Analogue test pin
A10
(Leave unconnected)
ANA_2
Analogue test pin
B04
(Leave unconnected)
ANA_3
Analogue test pin
C10
(Leave unconnected)
ANA_4
Analogue test pin
D09
(Leave unconnected)
AF_PRG
K10 Test pin (Leave unconnected) I/O
Open Open
1. To be strapped to VSS_ANA
Configuration pins
The configuration pins are used to select different modes of operation for the chip:
Table 14. STLC2500A configuration pins
Configuration
Description
Digital or analogue incoming system clock
CONFIG_CLK =’1’
The incoming system clock is a digital square signal.
(See Section 2.4)
CONFIG_CLK =’0’
The incoming system clock is a sine wave signal.
(See Section 2.4)
Initiated deep sleep modes
CONFIG_JS =’0’ AND
CONFIG_M = ‘0’
CONFIG_JS =’0’ AND
CONFIG_M = ‘1’
CONFIG_JS =’1’ AND
CONFIG_M = ‘0’
CONFIG_JS =’1’ AND
CONFIG_M = ‘1’
Reserved
Initiated Deep Sleep, mode 1. (See Section 6.8)
Initiated Deep Sleep, mode 2. (See Section 6.8)
Reserved
Where '1' means VDD_IO_A and '0' means VSS_DIG.
The other two configuration pins, CONFIG_RF and CONFIG_R have to be strapped to
VSS_DIG.
15/37
Share Link: 
