STLC2500A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC2500A' PDF : 37 Pages View PDF
STLC2500A
Figure 10. PCM (A-law, µ-law) standard mode
PCM_CLK
PCM_SYNC
PCM_A
PCM_B
01
15
125 µs
Figure 11. Linear mode
PCM_CLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
PCM_SYNC
PCM_A
PCM_B
125µs
Figure 12. Multi-slot operation
Digital interfaces
D02TL559
The PCM implementation supports from 1 up to 3 slots per frame with the following
parameters:
Table 20. PCM interface parameters
Symbol
Parameter
PCM interfaces
FPCM_CLK Frequency of PCM_CLK
FPCM_SYNC Frequency of PCM_SYNC
Psync_delay Delay of the starting of the first slot
Pclk_number
PCM_CLK is available during this
number of clock cycles
Min.
140 (1)
0
0
Typ.
2048
8
Max.
Unit
4000
255
255
kHz
kHz
cycles
cycles
31/37
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