STLC2500A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC2500A' PDF : 37 Pages View PDF
Digital interfaces
STLC2500A
Table 20. PCM interface parameters
Symbol
Parameter
Ss
Slot start (programmable for every
slot)
D
Data size
N
Number of slots per frame
1. In master mode, the minimum frequency is 2 MHz
Table 21. PCM interface timing
Symbol
Parameter
tWCH
tWCL
tWSH
tSSC
tSDC
tHCD
tDCD
High period of PCM_CLK
Low period of PCM_CLK
High period of PCM_SYNC
Setup time, PCM_SYNC high to
PCM_CLK low
Setup time, PCM_A/B input valid to
PCM_CLK low
Hold time, PCM_CLK low to
PCM_A/B input valid
Delay time, PCM_CLK high to
PCM_A/B output valid
Figure 13. PCM interface timing
tWCL
PCM_CLK
tWCH
tSSC
Min.
0
8
1
Min.
200
200
200
100
100
100
Typ.
Typ.
Max.
255
16
3
Max.
150
PCM_SYNC
tWSH
tSDC
tHCD
PCM_A/B in
PCM_B/A out
MSB
MSB-1 MSB-2 MSB-3 MSB-4
tDCD
MSB
MSB-1 MSB-2 MSB-3 MSB-4
D02TL557
Unit
cycles
bit
Unit
ns
ns
ns
ns
ns
ns
ns
7.3
JTAG interface
The JTAG interface is compliant with the JTAG IEEE Standard 1149.1. It allows both the
boundary scan of the digital pins and the debug of the ARM7TDMI application when
connected with the standard ARM7 developments tools. It is also used for the industrial test
of the device.
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