STLC90114 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC90114' PDF : 8 Pages View PDF
STLC90114 - STLC90115
4.2.2 Modem/Framer/Controller (STLC90115)
Figure 3. A block diagram of the DMT modem, framer and controller (STLC90115) showing the
receive and transmit paths.
35.3 Msps
14 bit
35.3 Msps
15 bit
000000000000000000000000000000000000000000000000ff000000000000rroo000000000000DDnn000000000000TRTSS000000000000ttixxm000000000000eePP000000000000nni000000000000ndd000000000000g000000000000000000000000u000000000000n000000000000it000000000000IsFF000000000000F000000000000F000000000000TT000000000000000000000000000000000000000000000000000000000000ppFF000000000000rr000000000000rrddooDee000000000000oocc000000000000qqPmmee000000000000uuL000000000000sseeaaL000000000000ssnnii000000000000nniinncc000000000000ggyy000000000000000000000000000000000000000000000000000000000000000000000000RRd000000000000000000000000SSein000000000000FFitn000000000000derret000000000000aaener000000000000mmlccre000000000000looeaii000000000000nndd000000000000avggii000000000000innvn,,000000000000iggng000000000000000000000000g&&000000000000000000000000000000000000000000000000000000000000000000000000000000000000AA000000000000TTll000000000000aaRMM000000000000Tyy000000000000xxee000000000000TTrr000000000000CC000000000000A000000000000R000000000000000000000000M000000000000000000000000000000000000U000000000000I000000000000t000000000000&o000000000000p000000000000IiIa000000000000000000000000000000000000000000000000000000000000 Utopia I or II
DiVA
PMD layer
PMS-TC layer
TPS-TC layer
The STLC90115 can be used in a hardware implementation for both central office (VTU-O) and remote
applications (VTU-R). No special mode setting is required, due to the programmability of the different func-
tions. In the STLC90115 the receive (RX) and transmit (TX) paths are separated.
Common parts are OBC or OCC, performance monitor and test functions. Control and configuration of the
STLC90115 is by an external processor. All programmable coefficients and parameters are loaded by the
OBC or OCC.
The VDSL initialization procedure is also controlled by the OBC or OCC. Such rapid control functions as
pilot tone tracking and the DMT symbol time alignment are implemented in the hardware. (e.g. a DPLL
with programmable filters and gains.)
Receive path
STLC90115 functions in the receive direction:
– Decimation of the RX signal (35.328 MHz) to a sampling rate of 17.664
– Receive Windowing
– Time domain to Frequency conversion with FFT
– Radio Frequency Interference Canceling
– Rotor and Frequency domain Equalizing
– Demapping of the DMT carriers to a digital bit stream
– Error and noise monitoring on individual carriers and pilot tones
– DPLL function for tracking the received signal frequency deviations
– Adaptive FEQ coefficient update scheme
– Reed Solomon decoding and de-interleaving
– Cell specific functions
– Utopia level 1 & 2 interface (& SLAP interface)
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