STM32F373C8 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STM32F373C8
STMicroelectronics
'STM32F373C8' PDF : 131 Pages View PDF
STM32F373xx
Electrical characteristics
6.3.18 DAC electrical specifications
Symbol
Table 63. DAC characteristics
Parameter
Conditions
Min Typ
Max
Unit
VDDA
Analog supply voltage
-
2.4 -
3.6
V
VREF+
Reference supply voltage VREF+ must always be below VDDA
2.4 -
3.6
V
VSSA
Ground
-
0-
0
V
RLOAD(1) Resistive load
DAC
Connected to VSSA
5-
-
output
kΩ
buffer ON Connected to VDDA
25 -
-
RO(1)
Output Impedance
DAC output buffer OFF
--
15
kΩ
CLOAD(1) Capacitive load
Maximum capacitive load at DAC_OUT
pin (when the buffer is ON).
-
-
50
pF
It gives the maximum output excursion
DAC_OUT
min(1)
Lower DAC_OUT voltage of the DAC.
with buffer ON
It corresponds to 12-bit input code
0.2 -
-
V
(0x0E0) to (0xF1C) at VREF+ = 3.6 V
DAC_OUT Higher DAC_OUT
max(1)
voltage with buffer ON
and (0x155) and (0xEAB) at VREF+ =
2.4 V
- - VDDA – 0.2
V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
It gives the maximum output excursion
-
0.5
-
mV
DAC_OUT Higher DAC_OUT
max(1)
voltage with buffer OFF
of the DAC.
- - VREF+ – 1LSB V
DAC DC current
With no load, worst code (0xF1C) at
IDDVREF+(3) consumption in quiescent VREF+ = 3.6 V in terms of DC
--
220
µA
mode (Standby mode) consumption on the inputs
DAC DC current
With no load, middle code (0x800) on
the inputs
-
-
380
µA
IDDA(3)
consumption in quiescent
mode(2)
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
--
480
µA
consumption on the inputs
DNL(3)
INL(3)
Differential non linearity
Difference between two
consecutive code-1LSB)
Given for the DAC in 10-bit
configuration
Given for the DAC in 12-bit
configuration
Integral non linearity
(difference between
measured value at Code i
and the value at Code i
on a line drawn between
Code 0 and last Code
1023)
Given for the DAC in 10-bit
configuration
Given for the DAC in 12-bit
configuration
--
--
--
± 0.5
LSB
±2
LSB
±1
LSB
--
±4
LSB
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