Electrical characteristics
STM32F373xx
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 22.
Table 37. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ @VDD = VDDA
Max Unit
= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V
tWUSTOP
tWUSTANDB
Y
Wakeup from Stop
mode
Wakeup from
Standby mode
Regulator in run mode
Regulator in low
power mode
LSI and IWDG off
4.1
7.9
62.6
tWUSLEEP
Wakeup from Sleep
mode
After WFE instruction
3.9
6.7
53.7
3.8 3.7
6.1 5.7
49.2 45.7
6
3.6 4.5
5.4 8.6 µs
42.7 100
CPU
clock
cycles
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 12.
Symbol
Table 38. High-speed external user clock characteristics
Parameter(1)
Conditions
Min Typ Max Unit
fHSE_ext
User external clock source
frequency
CSS is on or
PLL is used
1
8
CSS is off,
PLL not used
0
VHSEH OSC_IN input pin high level voltage
-
0.7 VDD -
VHSEL OSC_IN input pin low level voltage
-
VSS
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
-
15
-
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
-
-
-
1. Guaranteed by design.
32
MHz
VDD
V
0.3 VDD
-
ns
20
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