STP16CPC26MTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STP16CPC26MTR' PDF : 28 Pages View PDF
Timing diagrams
STP16CPC26
8
Timing diagrams
The timing diagram shown in Figure 10: "Timing diagram" and the truth table in Table 7:
"Truth table" explain how to send data to the device. This can be summarized in the
following points:
LE and OE are level sensitive and not synchronized with the CLK signal
When LE is at low level, the latch circuit holds previous data
If LE is high level, data present in the shift register are latched
When OE is at low level, the status of the outputs OUT0 to OUT15 depends on the
data in the latch circuits
With OE at high level, all outputs are switched off independently on the data stored
in the latch circuits
Every rising edge of the CLK signal, a new data on SDI pin is sampled. This data is
loaded into the shift register, whereas a bit is shifted out from SDO
Figure 10: Timing diagram
Clock LE OE
_|¯ H
L
_|¯ L
L
_|¯ H
L
¯|_ X
L
¯|_ X
H
Serial-IN
Dn
Dn + 1
Dn + 2
Dn + 3
Dn + 3
Table 7: Truth table
OUT0 ............. OUT7 ................ OUT15 (1)
Dn ..... Dn - 7 ..... Dn -15
No change
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn + 2 ..... Dn - 5 ..... Dn -13
OFF
Notes:
(1) OUTn = ON when Dn = H, OUTn = OFF when Dn = L.
SDO
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
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DocID18469 Rev 6
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