STP16CPC26MTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STP16CPC26MTR' PDF : 28 Pages View PDF
STP16CPC26
Timing diagrams
Figure 11: Timing for clock signal, serial-in and serial out data
The correct sampling of the data depends on the stability of the data at SDI on the rising
edge of the clock signal and it is assured by a proper data setup and hold time (tSETUP1 And
tHOLD), as shown in Figure 11: "Timing for clock signal, serial-in and serial out data". The
same figure shows the propagation delay from CLK to SDO (tPLH/tPHL). Figure 12: "Timing
for clock signal serial-in data, latch enable, output enable and outputs" describes the setup
times for LE and OE signals (tSETUP2 and tSETUP3 respectively), the minimum duration of
these signals (tWLAT and tWENA respectively) and the propagation delay from CLK to OUTn,
LE to OUTn and OE to OUTn (tPLH1/tPHL1, tPLH2/tPHL2 and tPLH3/tPHL3 respectively). Finally
Figure 13: "Outputs" defines the turn-on and turn-off time (tr and tf) of the current
generators.
DocID18469 Rev 6
13/28
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