STV0196 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV0196' PDF : 23 Pages View PDF
STV0196B
PIN LIST
Pin Number
Pin Name Type
Pin Description
SIGNAL INPUTS
51, 52, 53, 54, 55, 56
57, 58, 59, 60, 61, 62
48
I [5..0]
Q [5..0]
M_CLK
I In Phase Component, at twice the symbol frequency (2Fs).
I In Quadrature Component, at twice the symbol frequency (2Fs).
I Master Clock Input, 2Fs. Sampling Clock of the External A to D Converters.
FRONT END CONTROLS
46
CLKREC O 1 Bit Control Signal for the External CLK VCO. It must be Low-pass Filtered.
44
AGC
O 1 Bit Control Signal for the External AGC. It must be Low-pass Filtered.
35
D60
O M_CLK Divided by 60
SIGNAL OUTPUTS
26, 25, 24, 23,
22, 21, 20, 19
29
30
33
D [7..0] O Output Data
CK_OUT O Output Byte Clock
STR_OUT O Output Synchronization Byte Signal
D/P
O Data/Parity Signal
34
ERROR
I2C MICRO INTERFACE
O Output Error Signal. Set in Case of uncorrected Block.
39
SCL
I Serial Clock
40
SDA
I/O Serial Data Bus
OTHER
47
1, 2, 5, 6, 13, 14, 15,
16, 17, 18, 63, 64
MODE
TEST
I 0 = Mode A, 1 = Mode B
O Reserved for Manufacturing Test. It must remain unconnected
3, 7, 9, 11, 28, 32,
37, 41, 42, 49
4, 8, 10, 12, 27,
31, 38, 43, 45, 50
36
VSS
VDD
NRES
I Ground References
I 3.3V Supply
I Negative Reset
BLOCK DIAGRAM
I[5...0]
Q[5...0]
CLKREC
NYQUIST
FILTER
TIMING
RECOVERY
CARRIER
OFFSET
MEASURE
DEROTATOR
DCO
CARRIER PHASE
TRACKING LOOP
AGC
AGC
LOCK
INDICATOR
C/N
INDICATOR
D60
M_CLK
SCL
SDA
DIVIDE BY 60
I2C BUS
INTERFACE
VITERBI DECODER
DEINTERLEAVER
REED SOLOMON DECODER
MODE
STV0196B
ENERGY DESCRAMBLER
VDD
VSS
D[7..0]
D/P
ERROR
STR_OUT
CK_OUT
3/23
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