STV0196 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV0196' PDF : 23 Pages View PDF
STV0196B
FUNCTIONAL DESCRIPTION (continued)
VIII - AGC CONTROL
The modulusof the input is compared to a program-
mable threshold; the difference is scaled by the
AGC coefficient, then integrated; the result is con-
verted into a pulse density modulation signal to
drive the AGC output ; it may be filtered by a simple
analogue filter to control the gain command of any
amplifier before the A to D converter.
The 8 integrator MSB’s may be read or written at
any time by the micro; when written, the LSB’s are
reset. The integrator value is the level of the AGC
output, after low pass filtering ; it gives an image of
the input signal power, whatever this signal is, and
can be used to point the antenna.
The coefficient may be reset by programmation; in
that case, the AGC reduces to a programmable
voltage synthesiser.
The AGC reference level ”m” value impacts the
value of the following functions :
- carrier to noise indicator (see paragraph VII)
- the carrier loop (see paragraph V.2)
- the timing loop (paragraph IV.2)
- carrier offset evaluator (paragraph VI)
Control Registers
Internal Addresses : Hex11
Iagc
0
011000
Invert Reserved
signal
AGC reference
level (”m”)
Internal Addresses : Hex12
AGC integrator value (signed)
(Read/write register)
Internal Addresses : Hex13
0
0
0
0
0
0
1
0
Reserved
G[2..0] :
AGC coefficient
The 8 bit signed value in the integrator is the image
of the AGC output; reading this value gives an
image of the RF signal power.
A constant error on the modulus leads to a ramp at
the output of the integrator with value :
AGC_Int = 2AGC_Coeff-16 . error
As a consequence, for the reset conditions, a con-
stant signal of null value (error = 24) should cause
the output AGC duty cycle to go from 100% to 0%
in 222 symbol periods, or 8.7ms at 20MBauds.
If Iagc is set, the sign of the integrator is inverted.
IX - VITERBI DECODER AND SYNCHRONIZATION
The convolutives codes are generated by the
polynoms Gx = 171oct and Gy = 133oct.
The Viterbi decoder computes for each symbol the
metrics of the four possible paths, proportional to
the square of the Euclidian distance between the
received I and Q and the theoretical symbol value.
The puncture rate and phase are estimated on the
error rate basis.
Five rates are allowed and may be enabled/dis-
abled through register programming :
1/2, 2/3, 3/4,5/6, 7/8.
In Mode B, 7/8 is replaced by 6/7.
For each enabled rate, the current error rate is
compared to a programmable threshold; if it is
greater, anotherphase (or anotherrate) is tried until
the good rate is obtained.
A programmable hysteresis is added to avoid to
loose the phase during short term perturbation.
The rate may also be imposed by the external
software, and the phase is incremented only on
micro request ; the error rate may be read at any
time in order to use other algorithm than imple-
mented.
The decoder is accessed via a set of 9 registers :
Threshold Registers (VTH0 to VTH4)
Internal Address : Hex1 (VTH0) to 5 (VTH4)
Reset Value : Hex20
Threshold
Value
VTH0 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 rate 1/2
VTH1 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
VTH2 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
VTH3 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
rate 2/3
rate 3/4
rate 5/6
VTH4 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0
rate 7/8
or 6/7
For each register, bits 6 to 0 represent an error rate
threshold : the average number of errors happen-
ing during 256 bit periods; the maximum program-
mable value is 127/256 (higher error rates are of
no practical use).
Puncture Rate Enable register
Internal Address : Hex09
Reset Value : Hex10 (Mode A)
0
0
0 E4 E3 E2 E1 E0
E4 : enablePuncturedRate 7/8(Mode A)or6/7(Mode B)
E3 : enable Punctured Rate 5/6
E2 : enable Punctured Rate 3/4
E1 : enable Punctured Rate 2/3
E0 : enable Basic Rate 1/2
11/23
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