STV0196 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV0196' PDF : 23 Pages View PDF
STV0196B
I2C BUS CHARACTERISTICS (see Figure 9)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
VIL Input Logic Low Voltage
VIH Input Logic High Voltage
See Note 1
-0.3
0.8 V
2.0
5.5 V
VOL Output Logic Low Voltage
VOH Output Logic High Voltage
CLOAD = 20pF, ILOAD = 2mA,
M_CLK = 60MHz, see Note 1 2.4
0.5 V
5.5 V
ILK Input Leakage Current
VIN = 0V to VDD, see Note 2
-10
10 µA
CIN Input Capacitance
3.5
pF
IOL Output Sink Current
VOL = 0.5V
10
mA
tSP Pulse W idt h of Spikes which must be
suppressed by the Input filter
0
50 ns
fSCL SCL Clock Frequency
tBUF Bus Free Time between a STOP and START
Condition
0
400 kHz
1.3
µs
tHD,STA Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
0.6
µs
tLOW
tHIGH
tSU,STA
tSU,STO
tHD,DAT
tSU,DAT
tR, tF
CB
Low Period of the SCL Clock
High Period of the SCL Clock
Set-up Time for a repeated START Condition
Set-up Time for STOP Condition
Data Hold Time
See Note 3
Data Set-up Time
See Note 4
Rise and Fall Time of both SDA and SCL See Note 5
signals
Capacitive Load for each Bus Line
1.3
0.6
0.6
0.6
0
100
20 +
0.1 CB
µs
µs
µs
µs
0.9 µs
ns
300 ns
400 pF
Notes : 1.
2.
3.
4.
5.
An impedance higher than 2kΩ is required when SDA and SCL are tied to a 5V ± 10% voltage line.
Leakage current exceeds ± 10µA when SDA and SCL are tied to a 5V ± 10% line.
A device must internally provide a hold time of at least 300ns for the SDA signal (refered to the VIH Min. of the SCL signal) in order
to bridge the undefined region of the falling edge of SCL.
The maximum tHD,DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement tSU,DAT ≥ 250ns must then be
met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the
(according
low period of the SCL signal,
to the standard-mode I2C bus
it must output the next data bit to
specification) before the SCL line
the SDA line
is released.
tR
Max.
+
tSU,DAT
=
1000
+250
=
1250ns
CB = total capacitance of one bus line in pF.
15/23
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