STV0196 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV0196' PDF : 23 Pages View PDF
STV0196B
ABSOLUTE MAXIMUM RATINGS
Maximum limits indicate where permanent device damages occur, continuous operation at these limits is
not intended and should be limited to those conditions specified in section ”DC Electrical Specifications”.
Symbol
Parameter
Value
Unit
VDD
VI
Vo
Tstg
Toper
PD
Power Supply (1)
Voltage on Input pins (2)
Voltage on Output pins
Storage Temperature
Operating Ambient Temperature
Power Dissipation
-0.3 to 4
V
-0.3 to VDD + 0.3 V
-0.3 to VDD +0.3 V
-40 to +150
oC
-10 to +85
oC
1.5
W
Notes : 1. All VDD to be tied together
2. SCL, SDA, NRES Pins can be tied to 5V ± 10% with an impedance ≥ 2kΩ (remark in these conditions the input leakage current
becomes higher than 10µA).
DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V, Tamb = 25oC unless otherwise specified)
Symbol
VDD
IDD
VIL
VIH
VIL
VIH
ILK
CIN
VOL
VOH
Parameter
Operating Voltage
Average Power Supply Current
Input Logic Low Voltage except M_CLK
Input Logic High Voltage except M_CLK
Input Logic Low Voltage for M_CLK
Input Logic High Voltage for M_CLK
Input Leakage Current
Input Capacitance
Output Logic Low Voltage
Output Logic High Voltage
Test conditions
0oC
0oC
≤
<
Toper
Toper
≤
<
70oC
85oC,
M_CLK
≤
55MHz
CLOAD = 20pF on all outputs,
M_CLK = 60MHz
M_CLK = 60MHz
M_CLK = 60MHz
VIN = 0V and VDD
CLOAD = 20pF, ILOAD = 2mA,
M_CLK = 60MHz
Min.
3.0
3.15
-0.3
2.0
-0.3
2.2
2.4
Typ.
3.3
3.3
300
Max.
3.6
3.45
480
0.8
3.6
0.8
3.6
10
3.5
0.5
Unit
V
V
mA
V
V
V
V
µA
pF
V
V
Note :This product doesn’t withstand the MIL 883C Norm at 2kV, but only at 1.5kV (all VDD tied together).
TIMING CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Unit
PRIMARY CLOCK (see Figure 4)
tM_CLK Master Clock Period
tHIGH
tLOW
tR
tF
Clock High Time
Clock Low Time
Clock Rising Edge
Clock Falling Edge
I[5:0],Q[5:0] INPUT SPECIFICATION S (see Figure 5)
tSU I,Q stable before M_CLK
tH I,Q stable after M_CLK
D60 OUTPUT CHARACTERISTICS (see Figure 6)
t60 D60 period
0oC
0oC
≤
<
Toper
Toper
≤
<
70oC
85oC
16.6
18.2
6
6
4
4
(Tm_clk * 60)
- 10
ns
ns
ns
ns
4
ns
4
ns
ns
ns
(Tm_clk*60) ns
+10
D[7:0],D/P,CK_OUT,STR_OUT,ERROR OUTPUT CHARACTERISTICS
Bit RS1 = 1 in register RS ( adr = 0x0A) (see Figure 7)
tCKSU D[7:0],D/P,STR_OUT,ERROR stable before CK_OUT Falling Edge
32
ns
tCKH D[7:0],D/P,STR_OUT,ERROR stable after CK_OUT Falling Edge
32
ns
Bit RS1 = 0 in register RS ( adr = 0x0A) (see Figure 8)
tCKSU D[7:0],D/P,STR_OUT,ERROR stable before CK_OUT Rising Edge
32
ns
tCKH D[7:0],D/P,STR_OUT,ERROR stable after CK_OUT Rising Edge
32
ns
14/23
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