STV0196 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV0196' PDF : 23 Pages View PDF
STV0196B
FUNCTIONAL DESCRIPTION (continued)
X - CONVOLUTIONAL DE-INTERLEAVER
This is a 204 x 12 convolutional interleaver in
Mode A ; the periodicity of 204 bytes for sync byte
is preserved.
The de-interleaver may beskipped (see RS register).
XI - REED-SOLOMON DECODER
AND DESCRAMBLER
The input blocks are 204 byte long with 16 parity
bytes in Mode A; the synchro byte is the first byte
of the block. Up to 8 byte errors may be fixed.
Code Generator polynom:
g(x) = (x - ω0) (x - ω1) (...) (x - ω15)
over the Galois Field generated by :
X8 + X4 + X3 + X2 + 1 = 0
Energy dispersal descrambler :
Output energy dispersal descrambler generator :
X15 + X14 + 1
The polynom is initialised every eight blocks with
the sequence 100101010000000. The synchro
words are unscrambled.
Control register : RS register
Internal Address : Hex0A
The reset value is written in each register cell
RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0
1
0
1
1
1
0
0
0
RS7 : De-interleaver Enable
If 1, the input flow is deinterleaved.
If 0, the flow is not affected.
RS6 : If 0, Output data are corrected bytes
(normal operating mode).
If1, OutputdataareReed-Solomoncorrection
bytes (error count mode) (see Note 1).
Figure 3
CK_OUT RS 0=0, RS 1=0
RS 0=1, RS 1=0
RS 0=0, RS 1=1
RS 0=1, RS 1 =1
No Error
Da ta
P a rity
RS5 : Reed-Solomon Enable
If 1, the input code is corrected.
If 0, no correction happens; all the data are
fed to the descrambler.
The error signal remains inactive.
RS4 : Descrambler Enable
If 1, the output flow from Reed-Solomon
decoder is descrambled.
If 0, the descrambler is desactived.
RS3 : Write Error Bit
If RS3=1, and uncorrectible error happens,
the MSB of the first byte following the sync
byte is forced to 1after descrambling.
RS2 : Super Synchro Suppression
If RS2=1, all synchro bytes are Hex47 in
mode A.
If RS2=0, the synchro is complemented
every 8th packet. It allows, when scrambler
is off, to provide RS coded signals for use
in low-cost SMATV interface.
RS1 : Output Clock Polarity
If RS1=0, data and control signals change
during high to low transition of CK_OUT.
If RS1=1, they change during the low to
high transition.
RS0 : Output Clock Configuration
If RS0=0, CK_OUT is continuous.
If RS0=1, CK_OUT remains low during the
parity bits.
Note 1 : When RS6 = 1, the output data are the correction bytes
applied to data incoming the Reed-Solomon block.
The number of bits at 1 in these output data represent
therefore the number of errors remaining at the output of
VITERBI decoder.
All null output data mean no error left after VITERBI
decoding.
Remark : Output datas are meaningless when error flag (Pin 34) is
set to high level.
Uncorre cte d P a cke t
Da ta
P a rity
No Error
Da ta
P a rity
D/P
S TR_OUT
ERROR
13/23
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