STV0299B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV0299B' PDF : 36 Pages View PDF
STV0299B
4 FUNCTIONAL DESCRIPTION (continued)
4.3 Timing Recovery
4.3.1 Timing Control
The loop is parametrized by two coefficients:
alpha_tmg and beta_tmg. alpha_tmg can take
values from 0 to 4, and beta_tmg from 0 to 7
(Register 0E).
When the parameter is 0, the actual coefficient
value is zero. The 8 MSBs of the frequency
accumulator may be read or written at any time by
the I2C bus—when written, all LSBs are reset.
The Symbol Frequency Registers (MSB, Middle
Bits and LSB) are in Addresses 1F, 20 and 21.
These must be programmed with the expected
symbol frequency.
The units are:
f---M---_---C---L--K--
220
Write mode is effective when writing the Middle Bit
Register. The MSB Register must be loaded
before the Middle Bit Register.
The value of the Timing Frequency Register, when
the system is locked, is an image of the frequency
offset. The unit is fS/219 (approx. 2 ppm). It should
be as close as possible to 0 (by adjusting symbol
frequency register value) in order to have a
symmetrical capture range. Reading it allows for
optimal trimming of the timing range (Register
1A).
The actual symbol frequency is:
fSact
=
(---f--M----_--C---L---K----⋅---f---s--_--r--e--g----)---+-----(--2-----⋅---f--s----⋅---T----m----g--_---r--e--g----)
220
where fs_reg is the content of the symbol frequency
register and Tmg_reg the content of the timing
frequency register.
Table 5:
beta_tmg
1
2
3
4
5
6
7
alpha_tmg
Natural Frequency for
fS = 20 Mbaud
0.66 kHz
0.93 kHz
1.32 kHz
1.86 kHz
2.63 kHz
3.72 kHz
5.26 kHz
4.3.2 Loop Equation
The timing loop may be considered as a second
order loop. The natural frequency and the
damping factor may be calculated using the
following formula:
fn = 5.2 ⋅ 10–6 fS m2 ⋅ β
where, fS is the symbol frequency, m2 is the AGC2
reference level and β is programmed by the timing
register:
β = 2beta_tmg
The damping factor is:
ξ = -0---.-1----3---4-----⋅-------m------2-----⋅---2----a--l-p---h--a---_--t--m---g--
2 beta_tmg
where m2 is the reference level of the AGC2
register.
Table 5 shows the natural frequency in DVB, with
nominal reference level m2 = 20, for different
values of beta_tmg and alpha_tmg, without noise.
4.3.3 Timing Lock Indicator
The timing lock indicator reports a value
dependent upon the signal-to-noise ratio and on
the signal lock state.
With an AGC2 Reference level m2 = 20, if the
timing lock indicator is above 48, the timing is
locked; if it is above 42, this shows that a QPSK
signal is present, either locked with low C/N
(<3.6 dB) or unlocked with higher C/N; the
ambiguity may be solved by changing on purpose
the timing frequency of 1%; if it was locked before,
the indicator should be now under 42.
The indicator needs 30K symbols for stabilization
from unlock to lock after a frequency change.
The timing lock registers - the Timing Lock Setting
Register and the Timing Lock Indicator Register -
are in Addresses 11 and 17.
1
2
3
4
Damping Factor
0.85
1.70
3.38
6.77
0.60
1.20
2.40
4.80
0.42
0.85
1.70
3.38
0.30
0.60
1.20
2.40
0.21
0.42
0.85
1.70
0.15
0.30
0.60
1.20
0.10
0.21
0.42
0.85
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