STV0299B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV0299B' PDF : 36 Pages View PDF
STV0299B
4 FUNCTIONAL DESCRIPTION (continued)
4.4 Carrier Recovery and Derotator Loop
The tracking range of the derotator is ± fM_CLK/2
(± fsampling/2). The initial frequency search may
therefore be performed on several MHz ranges
without reprogramming the tuner.
Three phase detectors are selectable using
software:
• Phase detector algorithm 0: This algorithm
should only be used for BPSK reception.
• Phase detector algorithm 1: This algorithm is
used with QPSK reception, over a small range
of capture phases and with a channel noise
value over 4.5 dB.
• Phase detector algorithm 2: For QPSK
reception, it is used after locking, to minimize
the bit error rate in low channel noise
conditions. Algorithm 2 is recommended for
most applications.
The loop is controlled through α and β
parameters.
The carrier loop control registers (the Alpha
Carrier Register, the Beta Carrier Register and the
Carrier Frequency Register) are in Addresses 13,
14, 22 and 23.
4.4.1 Loop Parameters
Like the timing loop, the carrier loop is a
second-order system where two parameters, α
and β, may be programmed with alpha_car and
beta_car respectively.
The natural frequency (fn) is:
fn = 7 ⋅ 10–6 ⋅ fM_CLK
(m2 ⋅ β) ------f---S-------
fM_CLK
The damping factor is:
ξ = 22 ⋅ 10–6 ⋅ α m------2-- ------f---S-------
β fM_CLK
⋅ ⋅ where α = (2+a) 2b 214, with b ≥ 1, and
⋅ β = (4+2c+d) 2e, with e ≥ 1. m2 is the reference
level in the AGC2 register.
4.4.2 Carrier Lock Detector
The carrier lock detector provides an indicator
with a high value when the carrier is locked,
dependent on the channel noise. When the carrier
is not locked, the indicator value is low.
The indicator value is compared to a
programmable 8-bit threshold (Register 15h). The
result of this comparison (1 if greater than the
threshold, else 0 if not) is written as the Carrier
Found flag (CF), and may be read in the status
register. The CF signal may be permanently
routed on the output LOCK (see Register 08h).
The Lock Detector Threshold Register and Lock
Detector Value Register are in Addresses 15 and
1C.
4.4.3 Derotator Frequency
The derotator frequency can be either measured
(read operation) or forced (write operation).
(freq)kHz
=
D-----e---r--o----t--_---f--r---e---q--
216
⋅
(
f
M_CLK ) k
H
z
Derot_freq is a 16-bit signed value.
The Derot_freq Registers are Registers 22 and
23.
4.4.4 Carrier Frequency Offset Detector
The carrier recovery loop features a carrier
frequency offset detector and two phase
detectors. When the carrier frequency offset
detector is enabled, the central loop frequency is
modified proportionally to the carrier offset. The
gain and time constants of the detector are set by
CFD[6:4] and CFD[3:2] respectively. When the
carrier loop is about to “phase lock” with the
carrier, the frequency detector stops automatically
and the phase lock is ensured by the selected
phase detector. This switchover point is
determined by the threshold CFD [1:0].
For stability reasons, the gain CFD [6:4] should
not exceed the coefficient e[3:0] of Register
BCLC.
The carrier frequency offset detector is in Address
12.
4.5 Noise Indicator
The noise indicator may be used to facilitate the
antenna pointing or to give an idea of the RF
signal quality and of the front-end installation
(dish, LNB, cable, tuner or ADC).
A simple C/N estimator can be easily
implemented by comparing the current indications
with a primarily-recorded look-up table.
The time constant ranges from 4 k to 256 k
symbols. The 16 MSB of the result may be read by
the microprocessor (Registers 24 and 25).
14/36
Share Link: 
