Electrical Characteristics
Table 9: SDRAM timing
Symbol
Min
Typ
tCK
41.67
tCH
tCK/2 - (tCK*0.0345)
tCK/2
tCL
tCK/2 - (tCK*0.0345)
tCK/2
tAC
tOH
0
tCMS
20.3
tCMH
20
tAS
20.7
tDS
20.1
tDH
21.8
tRCD
1
tRAS
2
tRC
4
tRP
2
tRRD1
2
tah
19.8
1. tRRD = Row active to row active delay
STV0684
Max
tCK/2 + (tCK*0.0345)
tCK/2 + (tCK*0.0345)
24.8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
ns
Note: 1 The SDRAM interface is designed to operate with SDRAM devices which are compliant with the
Intel SDRAM Specification Revision 1.7 November 1999. Speed grades 66, 100 and 133MHz are
compatible.
2 Above timing assumes 20pF load per pad.
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