STV0684
Electrical Characteristics
Figure 14: Input data latch cycles for NAND flash interface
CLE
CE_n
ALE
WE_n
IO[0:7]
tALS
tWC
tWP tWH
tDS tDH
DIN0
DIN1
tCLH
DIN511
Figure 15: Sequential output cycle after read for NAND flash interface
CE_n
tRC
tRP tREH
RE_n
tREA
IO[0:7]
Dout
Dout
Dout
tRR
RB_n
Figure 16: Status read cycle for NAND flash interface
CLE
CE_n
WE_n
RE_n
IO[0:7]
tCLS
tWP
tCLH
tCLS
tWHR
tDS tDH
70h
tRSTO
Status
35/49