STV0684
Electrical Characteristics
4.5.8 AC characteristics for NAND flash operation
Table 12: AC characteristics for NAND flash operation
Symbol
Parameter
tCLS
tCLH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tRR
tRP
tRC
tREA
tREH
tWHR
tR
tWB
tRST
CLE Set-up time
CLE Hold time
WE-n Pulse Width
ALE Set-up time
ALE Hold time
Data Set-up time
Data Hold time
Write Cycle time
WE_n High Hold time
Ready to RE_n Low
RE_n Pulse Width
Read Cycle time
RE_n Access time
RE_n High Hold time
WE_n High to RE_n Low
Data Transfer from Cell to Register
WE_n High to Busy
Device Resetting (Read)
Min
61.4
83.2
83.2
82.6
82.4
82.6
61.8
145.1
61.9
81
83.2
187.2
103.5
124.2
Typical
62.4
Max
83.2
83.2
83.2
62.4
145.6
62.4
83
35
104
124.8
41.6
43.2
25.015
215.3
5.015
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
Note: 1 All parameters relating to the CE_n signal are omitted as it is not enabled/disabled during execution
of any NAND flash operation i.e. it is permanently tied low.
2 All timings are worst case
3 Conforms to both Samsung and Toshiba specifications as outlined in datasheets.
4 The NAND flash timings detailed here are guaranteed by design.
5 The loading factor used for the characterization is equivalent to 40pF.
4.5.9
Compact flash timing
There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface,
direct mapped I/O transfer and memory access. The STV0684 will only support the memory
mapped mode.
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