STV6886 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV6886' PDF : 43 Pages View PDF
STV6886
2.2 PLL1
The PLL1 consists of a phase comparator, an ex-
ternal filter and a voltage-controlled oscillator
(VCO).The phase comparator is a “phase/frequen-
cy” type designed in CMOS technology. This kind
of phase detector avoids locking on wrong fre-
quencies. It is followed by a “charge pump”, com-
posed of two current sources : sunk and sourced
(typically I =1 mA when locked and I = 140 µA
when unlocked). This difference between lock/un-
lock allows smooth catching of the horizontal fre-
quency by PLL1. This effect is reinforced by an in-
ternal original slow down system when PLL1 is
locked, avoiding the horizontal frequency chang-
ing too quickly. The dynamic behavior of PLL1 is
fixed by an external filter which integrates the cur-
rent of the charge pump. A “CRC” filter is generally
used (see Figure 7 on page 25).
Figure 8.
H/HVIN 1
LOCKDET
INPUT
INTERFACE
COMP1
High
Low
Extracted
VSync
Figure 7.
PLL1F
7
1.8kΩ
10nF
The PLL1 is internally inhibited during extracted
vertical sync (if any) to avoid taking in account
missing pulses or wrong pulses on phase compa-
rator. Inhibition is obtained by stopping high and
low signals at the input of the charge pump block
(see Figure 8 on page 25).
Lock/Unlock
Status
Extracted
VSync
PLL1F R0 C0
7 65
CHARGE
PUMP
PLL
INHIBITION
HPOSITION
PHASE
ADJUST
VCO
I2C
HPOS
Adj.
OSC
Figure 9.
PLL1F
7
(Loop Filter)
(1.4V<V7<4.9V)
I0
I0
2
6
4 I0
R0
6.4V
1.6V
RS
FLIP FLOP
5
C0
6.4V
1.6V
0 0.875 TH
25/43
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