STV6886 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV6886' PDF : 43 Pages View PDF
STV6886
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by the charge and the
discharge of the capacitor, with a current propor-
tional to the current in the resistor. The typical
thresholds of the sawtooth are 1.6 V and 6.4 V.
The control voltage of the VCO is between 1.4 V
and 4.9 V (see Figure 9). The theoretical frequen-
cy range of this VCO is in the ratio of 1 to 3.5. The
effective frequency range has to be smaller due to
clamp intervention on the filter lowest value.
The sync frequency must always be higher than
the free running frequency. For example, when us-
ing a sync range between 25 kHz and 80 kHz, the
suggested free running frequency is 22 kHz.
PLL1 ensures the coincidence between the lead-
ing edge of the sync signal and a phase reference
REF1 obtained by comparison between the saw-
tooth of the VCO and an internal DC voltage Vb.
Vb is I2C adjustable between 2.9 V and 4.2 V (cor-
responding to ±10 %) (see Figure 10).
The STV6886 also includes a Lock/Unlock identifi-
cation block which senses in real time whether
PLL1 is locked or not on the incoming horizontal
sync signal. This information is available through
I2C, and also on pin 3 if HLock/Unlock option has
been set through Subaddress 02,D8.
Figure 10. PLL1 Timing Diagram
H O SC
Sawtooth 7/8 TH
REF1
HSync
1/8 TH
6.4V
Ref. for H Position
Vb
(2.9V<Vb<4.2V)
1.6V
Figure 11. PLL2 Timing Diagram
HOsc
Sawtooth
7/8TH
1/8 TH
6.4V
4.0V
1.6V
Flyback
Internally
shaped Flyback
HDrive
Ts
Duty Cycle
The phase comparator of PLL2 is followed by a
charge pump (typical output current: 0.5 mA).
The flyback input consists of an NPN transistor.
The input current must be limited to less than 5 mA
(see Figure 12).
Figure 12. Flyback Input Electrical Diagram
HFLY 12
500Ω
Q1
20kΩ
Phase REF1 is obtained by comparison between
the sawtooth and a DC voltage adjustable between
2.9 V and 4.2 V.
The PLL1 ensures the exact coincidence between the
signal phase REF and HSYNC. A ±10% TH phase
adjustment is possible around the 3.5V point.
2.3 PLL2
PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
the VCO, taking into account the saturation time
Ts (see Figure 11 on page 26)
GND 0V
The duty cycle is adjustable through I2C from 30 %
to 65 %. For a safe start-up operation, the initial
duty cycle (after power-on reset) is 65% in order to
avoid having too long a conduction period of the
horizontal scanning transistor.
The maximum storage time (Ts Max.) is (0.44TH-
TFLY/2). Typically, TFLY/TH is around 20 %, at
maximum frequency, which means that Ts max is
around 34 % of TH.
26/43
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