WIRELESS, SENSING & TIMING
SX1276/77/78/79
DATASHEET
Address
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x44
0x4B
0x4D
0x5B
0x5D
0x61
0x62
0x63
0x64
0x70
others
Register Name
FSK/OOK Mode
RegTimer2Coef
RegImageCal
LoRaTM Mode
RegTemp
RegLowBat
RegIrqFlags1
RESERVED
RegIrqFlags2
RegDioMapping1
RegDioMapping2
RegVersion
RegPllHop
Unused
RegTcxo
RegPaDac
RegFormerTemp
RegBitRateFrac
Unused
RegAgcRef
RegAgcThresh1
RegAgcThresh2
RegAgcThresh3
RegPll
RegTest
Reset Default
(POR) (FSK)
0x20
0x82
0x02
-
0x02
0x80
0x40
0x00
0x00
0x12
0x2D
0x09
0x84
-
0x00
0x13
0x0E
0x5B
0xDB
0xD0
-
Description
FSK Mode
LoRaTM Mode
Timer 2 setting
Image calibration engine con-
trol
Temperature Sensor value
Low Battery Indicator Settings
Status register: PLL Lock state,
Timeout, RSSI
RESERVED
Status register: FIFO handling
flags, Low Battery
Mapping of pins DIO0 to DIO3
Mapping of pins DIO4 and DIO5, ClkOut frequency
Semtech ID relating the silicon revision
Control the fast frequency hop-
ping mode
Unused
TCXO or XTAL input setting
Higher power settings of the PA
Stored temperature during the former IQ Calibration
Fractional part in the Bit Rate
division ratio
Unused
Adjustment of the AGC thresholds
Control of the PLL bandwidth
Internal test registers. Do not overwrite
Note
- Reset values are automatically refreshed in the chip at Power On Reset
- Default values are the Semtech recommended register values, optimizing the device operation
- Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 6.2
Rev. 4 - March 2015
©2015 Semtech Corporation
Page 92
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