SX8723
ZoomingADC™ for Pressure and Temperature Sensing
ADVANCED COMMUNICATIONS & SENSING
Output Code Format
The ADC output code is a 16-bit word in two's complement format (see Table 15). For input voltages outside the
range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions
smaller than 16 bits, the non-significant bits are forced to the values shown in Table 16. The output code,
expressed in LSBs, corresponds to:
OUTADC
=
216
⋅ VIN , ADC
VREF , ADC
⋅ OSR +1
OSR
(LSB)
Equation 17
Recalling equation 9, this can be rewritten as:
OUTADC
=
216
⋅ VIN
VREF , ADC
⋅ GDTOT
− GDoffTOT
⋅ VREF , ADC
VIN
⋅
OSR +1
OSR
(LSB)
Equation 18
where, from Equation 10and Equation 11, the total PGA gain and offset are respectively:
GDTOT = GD3 ⋅ GD2 ⋅ GD1 (V/V)
and:
GDoffTOT = GDoff3 + GD3 ⋅ GDoff2 (V/V)
ADC Input Voltage VIN,ADC
+2.46146V
+2.46138V
...
+75µV
0V
-75µV
...
-2.46146V
-2.46154V
% of Full Scale (FS)
+0.5⋅FS
...
...
...
0
...
...
...
-0.5⋅FS
Output in LSBs
+215-1=+32'767
+215-2=+32'766
...
+1
0
-1
...
-215-1=-32'767
-215=-32'768
Output Code in Hex
7FFF
7FFE
...
0001
0000
8FFF
...
8001
8000
Table 15 - Basic ADC Relationships (example for: VREF,ADC = 5V, OSR = 64, n = 16 bits)
SET_OSR[2:0]
SET_NELC = 00
SET_NELC = 01
SET_NELC = 10
SET_NELC = 11
000
1000000000
100000000
10000000
1000000
001
10000000
1000000
100000
10000
010
100000
10000
1000
100
011
1000
100
10
1
100
10
1
-
-
101
-
-
-
-
110
-
-
-
-
111
-
-
-
-
Table 16 - Last Forced LSBs in Conversion Output Registers for Resolution Settings Smaller than 16
bits (n < 16) (RegACOutMsb[7:0] & RegACOutLsb[7:0])
V1.5 © 2007 Semtech Corp.
26
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