SX8723 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8723' PDF : 53 Pages View PDF
SX8723
ZoomingADC™ for Pressure and Temperature Sensing
ADVANCED COMMUNICATIONS & SENSING
ZADC Registers
Bit
Name
7:0 OUT[7:0]
Bit
Name
7:0 OUT[15:8]
Bit
Name
7
START
6:5 SET_NELC[1:0]
4:2 SET_OSR[2:0]
1
CONT
0
-
Bit
Name
7:6 IB_AMP_ADC[1:0]
5:4 IB_AMP_PGA[1:0]
3:0 ENABLE[3:0]
Bit
Name
7:6 FIN[1:0]
5:4 PGA2_GAIN[1:0]
3:0 PGA2_OFFSET[3:0]
Bit
Name
7 PGA1_GAIN
6:0 PGA3_GAIN[6:0]
Bit
Name
7-
6:0 PGA3_OFFSET[6:0]
Bit
Name
7 BUSY
6 DEF
5:1 AMUX[4:0]
0 VMUX
Mode
r
Reset
00000000
LSB of the ADC result
Description
Table 21 - RegACOutLsb (0x50)
Mode
r
Reset
00000000
MSB of the ADC result
Description
Table 22 - RegACOutMsb (0x51)
Mode
rw
rw
rw
rw
r
Reset
0
01
010
0
0
Description
Starts an ADC conversion
Sets the number of elementary conversions
Sets the ADC over-sampling rate
Sets continuos ADC conversion mode
unused
Table 23 - RegACCfg0 (0x52)
Mode
rw
rw
rw
Reset
11
11
0000
Description
Bias current selection for the ADC
Bias current selection for the PGA
ADC and PGA stage enables
Table 24 - RegACCfg1 (0x53)
Mode
rw
rw
rw
Reset
00
00
0000
Description
ADC Sampling Frequency selection
PGA2 gain selection
PGA2 offset selection
Table 25 - RegACCfg2 (0x54)
Mode
rw
rw
Reset
0
0001100
PGA1 gain selection
PGA3 gain selection
Description
Table 26 - RegACCfg3 (0x55)
Mode
Reset
Description
rw
Mode
r
rw
rw
rw
0000000
PGA3 offset selection
Table 27 - RegACCfg4 (0x56)
Reset
0
0
00000
0
Description
ADC activity flag
Selects ADC & PGA default configuration
Input channel configuration selector
Reference source selector (VBATT = 0 or VREF = 1)
Table 28 - RegACCfg5 (0x57)
V1.5 © 2007 Semtech Corp.
30
www.semtech.com
Share Link: 
