SX8723E083TRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8723E083TRT' PDF : 53 Pages View PDF
SX8723
ZoomingADC™ for Pressure and Temperature Sensing
ADVANCED COMMUNICATIONS & SENSING
Registers
The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain
(RegAcCfg0 to 5), and two registers are used to store the output code of the analog-to-digital conversion
(RegAcOutMsb & Lsb).
Register Name
RegACOutLsb
RegACOutMsb
RegACCfg0
Default values:
RegACCfg1
Default values:
RegACCfg2
Default values:
RegACCfg3
Default values:
RegACCfg4
Default values:
RegACCfg5
Default values:
Bit Position
7
6
5
4
3
2
1
OUT[7:0]
OUT[15:8]
START
0
SET_NELC[1:0]
01
SET_OSR[2:0]
010
CONT
0
IB_AMP_ADC[1:0]
11
IB_AMP_PGA[1:0]
11
ENABLE[3:0]
0000
FIN[1:0]
00
PGA2_GAIN[1:0]
00
PGA2_OFFSET[3:0]
0000
PGA1_G
0
PGA3_GAIN[6:0]
0001100
-
PGA3_OFFSET[6:0]
0
0000000
BUSY
0
DEF
0
AMUX[4:0]
00000
0
-
0
VMUX
0
Table 1 - Peripheral Registers to Configure the Acquisition Chain (AC)
and to Store the Analog-to-Digital Conversion (ADC) Result
With:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OUT: (r) digital output code of the analog-to-digital converter. (MSB = OUT[15])
START: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0.
SET_NELC: (rw) sets the number of elementary conversions to 2 SET_NELC[1:0]. To compensate for offsets, the input signal is
chopped between elementary conversions (1,2,4,8).
SET_OSR: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SET_OSR[2:0]). OSR = 8, 16, 32, ..., 512,
1024.
CONT: (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1.
TEST: bit only used for test purposes. In normal mode, this bit is forced to 0 and cannot be overwritten.
IB_AMP_ADC: (rw) sets the bias current in the ADC to 0.25*(1+ IB_AMP_ADC[1:0]) of the normal operation current (25, 50, 75 or
100% of nominal current). To be used for low-power, low-speed operation.
IB_AMP_PGA: (rw) sets the bias current in the PGAs to 0.25*(1+IB_AMP_PGA[1:0]) of the normal operation current (25, 50, 75 or
100% of nominal current). To be used for low-power, low-speed operation.
ENABLE: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are
disabled are bypassed.
FIN: (rw) These bits set the over sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency,
the sampling frequency is given as: 11 500 kHz, 10 250 kHz, 01 125 kHz, 00 62.5 kHz.
PGA1_GAIN: (rw) sets the gain of the first stage: 0 1, 1 10.
PGA2_GAIN: (rw) sets the gain of the second stage: 00 1, 01 2, 10 5, 11 10.
PGA3_GAIN: (rw) sets the gain of the third stage to PGA3_GAIN[6:0]⋅1/12.
PGA2_OFFSET: (rw) sets the offset of the second stage between –1 and +1, with increments of 0.2. The MSB gives the sign
(0 → positive, 1 → negative); amplitude is coded with the bits PGA2_OFFSET[5:0].
PGA3_OFFSET: (rw) sets the offset of the third stage between –5.25 and +5.25, with increments of 1/12. The MSB gives the sign
(0 → positive, 1 → negative); amplitude is coded with the bits PGA3_OFFSET[5:0].
BUSY: (r) set to 1 if a conversion is running.
DEF: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary conversions,
over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one.
AMUX(4:0): (rw) AMUX(4) sets the mode (0 differential inputs, 1 single ended inputs with A0 = common reference) AMUX(3)
sets the sign (0 straight, 1 cross) AMUX(2:0) sets the channel.
VMUX: (rw) sets the differential reference channel (0 VBATT, 1 VREF).
(r = read; w = write; rw = read & write)
V1.5 © 2007 Semtech Corp.
17
www.semtech.com
Share Link: 
