XE8801A – SX8801R
11.1 Features
• Input port, 8 bits wide
• Each bit can be set individually for debounced or direct input
• Each bit can be set individually for pull-up or not
• Each bit is an interrupt request source on the rising or falling edge
• A system reset can be generated on an input pattern
• PA[0] and PA[1] can generate two events for the CPU, individually maskable
• PA[0] to PA[3] can be used as clock inputs for the counters/timers/PWM (product dependent)
• PA[0] can be used to enable the RC oscillator
11.2 Overview
Port A is a general purpose 8 bit wide digital input port, with interrupt capability. Figure 11-1 shows its structure.
VBat
Port A
8
8
8
8x
debounce
0
8
1
8
10
18
DebFast
0
(RegSysMisc(2)) 8x
8
8
1
11
PAReset[x]
10
01
0
00
8x
RegPAPullup
RegPADebounce
RegPACtrl
RegPAIn
RegPAEdge
RC
interrupts
events
cntclocks
256 Hz
8 kHz
RegPARes1
RegPARes0
resetfromporta
Figure 11-1:structure of Port A
© Semtech 2005
11-2
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