T89C51AC2-RLTIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'T89C51AC2-RLTIM' PDF : 121 Pages View PDF
A/T89C51AC2
Figure 19. External Code Fetch Waveforms
CPU Clock
ALE
PSEN#
P0 D7:0
PCL
P2 PCH
D7:0
PCH
PCL
D7:0
PCH
Flash Memory
Architecture
A/T89C51AC2 features two on-chip Flash memories:
• Flash memory FM0:
containing 32 KB of program memory (user space) organized into 128 byte pages,
• Flash memory FM1:
2 KB for boot loader and Application Programming Interfaces (API).
The FM0 can be program by both parallel programming and Serial In-System-Program-
ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP
mode is detailed in the "In-System-Programming" section.
All Read/Write access operations on Flash Memory by user application are managed by
a set of API described in the "In-System-Programming" section.
Figure 20. Flash Memory Architecture
Hardware Security (1 byte)
Extra Row (128 Bytes)
Column Latches (128 Bytes)
7FFFh
32 KB
Flash memory
user space
FM0
2 KB
Flash memory
boot space
FM1
FFFFh
F800h
FM1 mapped between F800h and
FFFFh when bit ENBOOT is set in
AUXR1 register
0000h
35
4127H–8051–02/08
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