Table 7. PCA SFRs (Continued)
Mnemonic Add Name
7
6
5
4
3
2
1
0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1 L
PCA Compare Capture Module 2 L
PCA Compare Capture Module 3 L
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Table 8. Interrupt SFRs
Mnemonic Add Name
IEN0
A8h
Interrupt Enable
Control 0
IEN1
E8h
Interrupt Enable
Control 1
IPL0
B8h
Interrupt Priority
Control Low 0
IPH0
B7h
Interrupt Priority
Control High 0
IPL1
F8h
Interrupt Priority
Control Low 1
IPH1
F7h
Interrupt Priority
Control High1
7
6
5
4
3
2
1
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
–
–
–
–
–
–
EADC
–
–
PPC
PT2
PS
PT1
PX1
PT0
PX0
–
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
–
–
–
–
–
–
PADCL
–
–
–
–
–
–
–
PADCH
–
Table 9. ADC SFRs
Mnemonic Add Name
ADCON
F3h ADC Control
ADCF
F6h ADC Configuration
ADCLK
F2h ADC Clock
ADDH
F5h ADC Data High byte
ADDL
F4h ADC Data Low byte
7
–
CH7
–
ADAT9
–
6
PSIDLE
CH6
–
ADAT8
–
5
ADEN
CH5
–
ADAT7
–
4
ADEOC
CH4
PRS4
ADAT6
–
3
ADSST
CH3
PRS3
ADAT5
–
2
SCH2
CH2
PRS2
ADAT4
–
1
SCH1
CH1
PRS1
ADAT3
ADAT1
0
SCH0
CH0
PRS0
ADAT2
ADAT0
Table 10. Other SFRs
Mnemonic Add Name
PCON
87h Power Control
AUXR
8Eh Auxiliary Register 0
AUXR1
A2h Auxiliary Register 1
CKCON 8Fh Clock Control
FCON
D1h Flash Control
EECON D2h EEPROM Contol
7
SMOD1
–
–
–
FPL3
EEPL3
6
SMOD0
–
–
WDX2
FPL2
EEPL2
5
–
M0
ENBOOT
PCAX2
FPL1
EEPL1
4
POF
–
–
SIX2
FPL0
EEPL0
3
GF1
XRS1
GF3
T2X2
FPS
–
2
GF0
XRS2
0
T1X2
FMOD1
–
1
PD
EXTRAM
–
T0X2
FMOD0
EEE
0
IDL
A0
DPS
X2
FBUSY
EEBUSY
12 A/T89C51AC2
4127H–8051–02/08