T89C51AC2-SLSIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'T89C51AC2-SLSIM' PDF : 121 Pages View PDF
A/T89C51AC2
Figure 9. Power-down Exit Waveform Using INT1:0#
INT1:0#
OSC
Active phase
Power-down phase
Oscillator restart phase
Active phase
2. Generate a reset.
– A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the T89C51CC02 and vectors
the CPU to address 0000h.
Notes:
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
RAM content.
Table 14. Pin Conditions in Special Operating Modes
Mode
Port 0
Port 1
Port 2
Port 3
Reset
Floating
High
High
High
Idle
(internal
code)
Idle
(external
code)
Data
Floating
Data
Data
Data
Data
Data
Data
Power-
Down(inter
nal code)
Data
Data
Data
Data
Power-
Down
(external
code)
Floating
Data
Data
Data
Port 4
High
Data
Data
Data
Data
ALE
High
High
PSEN#
High
High
High
High
Low
Low
Low
Low
21
4127H–8051–02/08
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