Figure 14. External Data Read Waveforms
CPU Clock
ALE
RD 1
P0
DPL or Ri
D7:0
P2 P2
DPH or P22
Notes: 1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
Figure 15. External Data Write Waveforms
CPU Clock
ALE
WR1
P0
P2 P2
DPL or Ri
D7:0
DPH or P22
Notes: 1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
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