T89C51AC2-SLSIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'T89C51AC2-SLSIM' PDF : 121 Pages View PDF
A/T89C51AC2
Bit
Bit
Number Mnemonic Description
Internal/External RAM (00h - FFh)
1
EXTRAM
access using MOVX @ Ri/@ DPTR
0 - Internal XRAM access using MOVX @ Ri/@ DPTR.
1 - External data memory access.
Disable/Enable ALE)
0
A0
0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used)
1 - ALE is active only during a MOVX or MOVC instruction.
Reset Value = X00X 1100b
Not bit addressable
Table 20. AUXR1 Register
AUXR1 (S:A2h)
Auxiliary Control Register 1
7
6
5
4
3
2
1
0
-
-
ENBOOT
-
GF3
0
-
DPS
Bit
Number
7-6
5
4
3
2
1
0
Bit
Mnemonic Description
-
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Enable Boot Flash
ENBOOT(1) Set this bit for map the boot Flash between F800h -FFFFh
Clear this bit for disable boot Flash.
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
GF3 General-purpose Flag 3
Always Zero
0
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
-
Reserved for Data Pointer Extension.
DPS
Data Pointer Select Bit
Set to select second dual data pointer: DPTR1.
Clear to select first dual data pointer: DPTR0.
Reset Value = XXXX 00X0b
Note: 1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming
section.
29
4127H–8051–02/08
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