Table 31. Read MOVC A, @DPTR
FCON Register
Code Execution FMOD1 FMOD0 FPS
ENBOOT
DPTR
FM1
FM0
XROW
Hardware External
Byte
Code
0
0000h to 7FFFh
OK
0
0
X
0000h to 7FFFh
1
F800h to FFFFh
OK
Do not use this configuration
0
1
X
From FM0
1
0
X
0000 to 007Fh
X
See (1)
X
X
OK
OK
0
000h to 7FFFh
OK
1
1
X
0000h to 7FFFh
1
F800h to FFFFh
OK
Do not use this configuration
0000h to 7FFF
OK
1
0
F800h to FFFFh
OK
0
0
0
X
NA
1
From FM1
(ENBOOT =1
0
1
X
1
X
0
X
1
0000h to 007h
0
See (2)
OK
NA
OK
NA
1
1
0
X
X
0
OK
NA
1
1
X
1
000h to 7FFFh
0
OK
NA
External code :
EA=0 or Code
X
0
X
X
X
OK
Roll Over
1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to
007Fh
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to
007Fh
46 A/T89C51AC2
4127H–8051–02/08