T89C51AC2-SLSIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'T89C51AC2-SLSIM' PDF : 121 Pages View PDF
A/T89C51AC2
Serial I/O Port
The A/T89C51AC2 I/O serial port is compatible with the I/O serial port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
Figure 27. Serial I/O Port Block Diagram
IB Bus
TXD
Write SBUF
SBUF
Transmitter
Mode 0 Transmit
SBUF
Receiver
Read SBUF
Load SBUF
RXD
Receive
Shift register
Serial Port
Interrupt Request
RI TI
SCON reg
Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register.
Figure 28. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI
RI
Set FE bit if stop bit is 0 (framing error)
SM0 to UART mode control
SMOD1SMOD0 -
POF GF1 GF0 PD IDL
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register bit is set.
The software may examine the FE bit after each reception to check for data errors.
Once set, only software or a reset clears the FE bit. Subsequently received frames with
valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the
stop bit instead of the last data bit (See Figure 29. and Figure 30.).
51
4127H–8051–02/08
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