T89C51AC2-SLSIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'T89C51AC2-SLSIM' PDF : 121 Pages View PDF
A/T89C51AC2
Mode 2 (8-bit Timer with Auto-
Reload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads
from TH0 register (see Figure 33). TL0 overflow sets TF0 flag in TCON register and
reloads TL0 with the contents of TH0, which is preset by software. When the interrupt
request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next
reload value may be changed at any time by writing it to TH0 register.
Figure 33. Timer/Counter x (x = 0 or 1) in Mode 2
See the “Clock” section
FTx
CLOCK
Tx
INTx#
÷6
0
1
C/Tx#
TMOD reg
GATEx
TMOD reg
TRx
TCON reg
TLx
(8 bits)
Overflow
TFx
TCON reg
Timer x
Interrupt
Request
THx
(8 bits)
Mode 3 (Two 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (see Figure 34). This mode is provided for applications requiring an additional 8-
bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-
ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a
Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and
run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode
3.
Figure 34. Timer/Counter 0 in Mode 3: Two 8-bit Counters
FTx
CLOCK
÷6
0
1
T0
INT0#
C/T0#
TMOD.2
TL0
(8 bits)
Overflow
TF0
TCON.5
Timer 0
Interrupt
Request
GATE0
TMOD.3
TR0
TCON.4
FTx
CLOCK
÷6
See the “Clock” section
TR1
TCON.6
TH0
(8 bits)
Overflow
TF1
TCON.7
Timer 1
Interrupt
Request
59
4127H–8051–02/08
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