TCS3404 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
MFG CO.
'TCS3404' PDF : 56 Pages View PDF
TCS3404, TCS3414 − Principles of Operation
Principles of Operation
Analog-to-Digital Converter
The TCS3404/14 contains four integrating analog-to-digital
converters (ADC) that integrate the currents from the four
photodiodes (channel 1 through channel 4). Integration of all
four channels occurs simultaneously, and upon completion of
the conversion cycle the conversion results are transferred to
the channel data registers, respectively. The transfers are
double-buffered to ensure that invalid data is not read during
the transfer. After the transfer, the device automatically begins
the next integration cycle.
There are two ways to control the integration cycles: internally
timed and externally timed. Internally-timed integration cycles
can either be continuous back-to-back conversions or can be
externally triggered as a single event using the SYNC pin.
Externally-timed integrations can be controlled by setting and
clearing a register bit (i.e. ADC_EN in Control Register) using the
serial interface, or by 1 or more pulses input to the SYNC pin.
Integration options are configured through the Timing Register
(see Timing Register (01h) for more information).
Digital Interface
Interface and control of the TCS3404/14 is accomplished
through a two-wire serial interface to a set of registers that
provide access to device control functions and output data. The
serial interface is compatible with System Management Bus
(SMBus) versions 1.1 and 2.0, and I2C bus Fast-Mode.
The TCS3404/14 device supports a single slave address outlined
in Figure 24. Additional devices shown in the Ordering
Information support additional I2C slave addresses for systems
requiring more than one device.
Figure 24:
Slave Address
Slave Address
0111001
SMB Alert Address
0001100
Note(s):
1. The slave and SMB Alert addresses are 7 bits. Please note the SMBus and I2C
protocols on the following pages. A read/write bit should be appended to
the slave address by the master device to communicate properly with the
device.
ams Datasheet
[v1-00] 2015-Nov-11
Page 15
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