TCS3413 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
MFG CO.
'TCS3413' PDF : 56 Pages View PDF
TCS3404, TCS3414 − Principles of Operation
Figure 38:
Interrupt Control Register
7
Resv
6
INTR_STOP
5
4
INTR
3
Resv
2
1
0
PERSIST
Field
Resv
INTR_STOP
INTR
Resv
PERSIST
Bits
7
6
5:4
3
2:0
Description
Reserved. Write as 0.
Stop ADC integration on interrupt. When high, ADC integration will stop once an
interrupt is asserted. To resume operation (1) de-assert ADC_EN using Control
Register, (2) clear interrupt using Command Register, and (3) re-assert ADC_EN
using Control Register. (1)
INTR Control Select. This field determines mode of interrupt logic according to the
table below:
Field Value
Interrupt Control
00
Interrupt output disabled.
01
Level Interrupt.
10
SMB-Alert compliant.
11
Sets an interrupt and functions as mode 10.
See note (2)
Reserved. Write as 0.
Interrupt persistence. Controls rate of interrupts to the host processor:
Field Value
000
001
Timer
Every
Single
Description
Every ADC cycle generates interrupt
Any value outside of threshold range
010
0.1 sec Consecutively out of range for 0.1 second
011
1 sec
Consecutively out of range for 1 second
Note(s):
1. Use this bit to isolate a particular condition when the sensor is continuously integrating.
2. Value 11 may be used to test interrupt connectivity in a system or to assist in debugging interrupt service routine software. See
Application Information: Software section for further information.
ams Datasheet
[v1-00] 2015-Nov-11
Page 27
Document Feedback
Share Link: 
