TCS3413 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
MFG CO.
'TCS3413' PDF : 56 Pages View PDF
TCS3404, TCS3414 − Principles of Operation
Gain Register (07h)
The Gain Register provides a common gain control adjustment
for all four parallel ADC output channels. Two gain bits [5:4] in
the Gain Register allow the relative gain to be adjusted from 1×
to 64× in 4× increments. The advantage of the gain adjust is to
extend the dynamic range of the light input up to a factor of
64× before analog or digital saturation occurs. If analog
saturation has occurred, lowering the gain sensitivity will likely
prevent analog saturation especially when the integration time
is relatively short. For longer integration times, the 16-bit
output could be in digital saturation (64K). If lowering the gain
to 1× does not prevent digital saturation from occurring, the
use of PRESCALER can be useful.
The PRESCALER is 3 bits [2:0] in the Gain Register that divides
down the output count (i.e. shifts the LSB of the count value to
the right). The PRESCALER adjustment range is divide by 1 to
64 in multiples of 2.
The most sensitive gain setting of the device would be when
GAIN is set to 11b (64×), and PRESCALER is set to 000b (divide
by 1). The least sensitive part setting would be GAIN 00 (1×) and
PRESCALER 110 (divide by 64). If the part continues to be in
digital saturation at the least sensitive setting, the integration
time can be lowered (see Timing Register (01h) section).
ams Datasheet
[v1-00] 2015-Nov-11
Page 29
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