TCS3415 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
MFG CO.
'TCS3415' PDF : 56 Pages View PDF
TCS3404, TCS3414 − Principles of Operation
Interrupt Control Register (02h)
The Interrupt Register controls the extensive interrupt
capabilities of the device. The open-drain interrupt pin is active
low and requires a pullup resistor to VDD in order to pull high
in the inactive state. Using the Interrupt Source Register (03h),
the interrupt can be configured to trigger on any one of the four
ADC channels. The TCS3404/14 permits both SMB-Alert style
interrupts as well as traditional level style interrupts. The
Interrupt Register provides control over when a meaningful
interrupt will occur. The concept of a meaningful change can be
defined by the user both in terms of light intensity and time, or
persistence of that change in intensity. The value must cross
the threshold (as configured in the Threshold Registers 08h
through 0Bh) and persist for some period of time as outlined in
the table below.
When a level Interrupt is selected, an interrupt is generated
whenever the last conversion results in a value outside of the
programmed threshold window. The interrupt is active-low and
remains asserted until cleared by writing an 11 in the
TRANSACTION field in the Command Register.
In SMB-Alert mode, the interrupt is similar to the traditional
level style and the interrupt line is asserted low. To clear the
interrupt, the host responds to the SMB-Alert by performing a
modified Receive Byte operation, in which the Alert Response
Address (ARA) is placed in the slave address field, and the
TCS3404/14 that generated the interrupt responds by returning
its own address in the seven most significant bits of the receive
data byte. If more than one device connected on the bus has
pulled the SMBAlert line low, the highest priority (lowest
address) device will win control of the bus during the slave
address transfer. If the device loses this arbitration, the
interrupt will not be cleared. The Alert Response Address is 0Ch.
When INTR = 11, the interrupt is generated immediately
following the SMBus write operation. Operation then behaves
in an SMB-Alert mode, and the software set interrupt may be
cleared by an SMB-Alert cycle.
Page 26
Document Feedback
ams Datasheet
[v1-00] 2015-Nov-11
Share Link: 
