TDA7491MV View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7491MV' PDF : 28 Pages View PDF
Application information
TDA7491MV
7.4
7.4.1
7.4.2
Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an
external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all
devices operate at the same clock frequency. This can be implemented by using one
TDA7491MV as master clock, while the other devices are in slave mode (that is, externally
clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.
Master mode (internal clock)
Using the internal oscillator, the output switching frequency, fSW, is controlled by the
resistor, ROSC, connected to pin ROSC:
fSW = 106 / ((16 * ROSC + 182) * 4) kHz
where ROSC is in k.
In master mode, pin SYNCLK is used as a clock output pin, whose frequency is:
fSYNCLK = 2 * fSW
For master mode to operate correctly then resistor ROSC must be less than 60 k as given
below in Table 9.
Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating.
This forces pin SYNCLK to be internally configured as an input as given in Table 9.
The output switching frequency of the slave devices is:
fSW = fSYNCLK / 2
Mode
Master
Slave
Table 9. How to set up SYNCLK
ROSC
ROSC < 60 k
Floating (not connected)
SYNCLK
Output
Input
Figure 22. Master and slave connection
Master
Slave
TDA7491M
TDA7491M
ROSC
SYNCLK
Output
SYNCLK
Input
ROSC
Cosc
100 nF
Rosc
39 k
22/28
DocID14576 Rev 4
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