TDA7580 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7580' PDF : 31 Pages View PDF
RDS SPI interface
4
RDS SPI interface
Figure 10. RDS SPI timings
SS
MISO
MOSI
SCL
(CPOL=0,CPHA=0)
Valid
tdtr
tsetup
tsssetup
tsclkl
thold
tsclkh
tsclk
TDA7580
tsshold tssw
Table 18.
Symbol
RDS SPI timing table
(Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The
values on the table are consistent with a capacitance load on RDS SPI lines of
80pF
Description
Min
Typ
Max Unit
Slave configured
tsclk
tdtr
tsetup
thold
tsclkh
tsclkl
tsssetup
tsshold
tssw
Clock cycle
Sclk edge to MISO valid
MOSI setup time
MOSI hold time
SCK high time width
SCK low time width
SS setup time
SS hold time
SS pulse width
1240
239
255
365
620
620
620
620
1240
ns
365
ns
ns
ns
ns
ns
ns
ns
ns
22/39
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