TDA7580 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7580' PDF : 31 Pages View PDF
TDA7580
7
I2C timing
Figure 16. DSP and RDS I2C BUS timings
I2C timing
Table 21. I2C BUS timing table
(Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V)
Symbol
Parameter
Test
condition
Standard mode
I2C BUS
Min. Max.
Fast mode
I2C BUS
Unit
Min.
Max.
FSCL
tBUF
SCLl clock frequency
Bus free between a stop and start
condition
0
100
0
4800
–
1300
400 kHz
–
ns
Hold time (repeated) START condition.
tHD:STA After this period, the first clock pulse is
generated
4800
–
600
–
ns
tLOW
tHIGH
tSU:STA
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated start
condition
4800
–
1300
–
ns
4800
–
600
–
ns
4800
–
600
–
ns
tHD:DAT DATA hold time
0
-
0
900
ns
tR Rise time of both SDA and SCL signals Cb in pF
–
300 12+0.1Cb 300
ns
tF Fall time of both SDA and SCL signals Cb in pF
–
300 12+0.1Cb 300
ns
tSU;STO Set-up time for STOP condition
4800
–
600
–
ns
tSU:DAT Data set-up time
250
–
250
–
ns
Cb Capacitive load for each bus line
10
400
10
400
pF
27/39
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