TDA9105A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9105A' PDF : 31 Pages View PDF
TDA9105A
OPERATING DESCRIPTION (continued)
Figure 11 : Principle Diagram
H-LOCKCAP
13
H-LOCKOUT
2
PLL1INHIB PLL1F R0 C0
14
12 11 10
H-SYNC 17
INPUT
INTERFACE
LOCKDET
COMP1
E2
High
Low
CHARGE
PUMP
PLL
INHIBITION
VCO
H-POS
15
PHASE
ADJUST
3.2V
OSC
The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
charge pump. A “CRC” filter is generally used (see
Figure 9).
PLL1 is inhibited by applying a high level on Pin 14
(PLLinhib)which is a TTL compatibleinput. The inhibi-
tion results from the opening of a switch located be-
tween the charge pump and the filter (see Figure 8).
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by charge and dis-
charge of the capacitor, by a current proportionnal
to the current in the resistor. typical thresholds of
sawtooth are 1.6V and 6.4V (see Figure 10).
The control voltage of the VCO is typically com-
prised between 1.6V and 6V (see Figure 10). The
theoreticalfrequencyrangeof thisVCO isin the ratio
1 → 3.75, but due to spread and thermal drift of
external componentsand the circuit itself, the effec-
Figure 13 : Details of VCO
tive frequency range has to be smaller (e.g. 30kHz
→ 85kHz). In the absence of synchronisationsignal
the control voltageis equal to 1.6V typ.and the VCO
oscillates on its lowest frequency (free frequency).
The synchro frequencyhasto be alwayshigherthan
the free frequencyand a margin has to be taken. As
an example for a synchro range from 30kHz to
85kHz, the suggested free frequency is 27kHz.
Figure 12
PLL1F
12
Loop
Filter
12
(1.6V < V12 < 6V)
I0
2
I0
4 I0
2
11
R0
6.4V
1.6V
RS
FLIP FLOP
10 6.4V
C0
1.6V
0 0.75T T
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