TDA9106 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9106' PDF : 30 Pages View PDF
TDA9106
OPERATING DESCRIPTION (continued)
When the synchronization pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor, COSC = 150nF,
the typical free running frequency is 106Hz.
Typical free running frequency can be calculated
by :
f0
(Hz)
=
1.6
e−5
⋅
1
COSC
A negative or positive TTL level pulse applied on
Pin 33 (VSYNC) as well as a TTL composite sync
on Pin 38 or a Sync on Green signal on Pin 1 can
synchronise the ramp in the range [fmin , fmax].
This frequency range depends on the external
capacitor connected on Pin 27. A capacitor in the
range [150nF, 220nF] ± 5% is recommanded for
application in the following range : 50Hz to 120Hz.
Typical maximum and minimum frequency, at 25oC
and without any correction (S correction or C cor-
rection), can be calculated by :
f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0
If S or C corrections are applied, these values are
slighty affected.
If a synchronization pulse is applied, the internal
oscillator is automaticaly synchronized but the am-
plitude is no more constant. An internal correction
is activated to adjust it in less than a half a second
: the highest point of the ramp (Pin 27) is sampled
on the sampling capacitor connected on Pin 25 at
each clock pulse and a transconductanceamplifier
generates the charge current of the capacitor. The
ramp amplitude becomes again constant and fre-
quency independant.
The read status register enables to have the verti-
cal Lock-Unlock and the vertical Sync Polarity in-
formations.
It is recommandedto use a AGC capacitor with low
leakage current. A value lower than 100nA is man-
datory.
Good stability of the internal closed loop is reached
by a 470nF ± 5% capacitor value on Pin 25 (VAGC).
Pin 30, VFLY is the vertical flyback input used to
generate the vertical blanking signal on Pin 23. If
Vfly is not used, (VREF - 0.5), at minimum, must be
connected to this input.
In such case, the vertical blanking output will be
activated by the vertical sync input signal and re-
setted by the end of vertical sawtooth discharging
pulse.
III.6 - I2C Control Adjustments
Then, S and C correction shapes can be added to
this ramp. This frequency independent S and C
corrections are generated internally. Their ampli-
tude are adjustable by their respective I2C register.
They can also be inhibited by their Select bit.
At the end, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp ampli-
tude control register.
The adjusted ramp is available on Pin 29 (VOUT) to
drive an external power stage.
The gain of this stage is typically 25% depending
on its register value.
The DC value of this ramp is kept constant in the
frequency range, for any correction applied on it.
its typical value is VMID = 7/16 ⋅ VREF.
A DC voltage is available on Pin 28 (VDCOUT). It
is driven by its own I2C register (vertical Position).
Its value is VDCOUT = 7/16 ⋅ VREF ± 300mV.
So the VDCOUT voltage is correlated with DC value
of VOUT. It increases the accuracy when tempera-
ture varies.
III.7 - Basic Equations
In first approximation,the amplitude of the ramp on
Pin 29 (Vout) is :
VOUT - VMID = (VOSC - VMID) ⋅ (1 + 0.25 (VAMP))
with VMID = 7/16 ⋅ VREF ; typically 3.5V, the middle
value of the ramp on Pin 27
VOSC = V27 , ramp with fixed amplitude
VAMP is -1 for minimum vertical amplitude register
value and +1 for maximum
On Pin 28 (VDCOUT), the voltage (in volts) is calcu-
lated by :
VDCOUT = VMID + 0.3 (VPOS)
with VPOS equals -1 for minimum vertical position
register value and +1 for maximum
The current available on Pin 27 is :
IOSC
=
3
8
⋅
VREF ⋅
COSC
⋅
f
with COSC : capacitor connected on Pin 27
f : synchronization frequency
26/30
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