TDA9106A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9106A' PDF : 30 Pages View PDF
TDA9106A
OPERATING DESCRIPTION (continued)
II - HORIZONTAL PART
II.1 - Internal Input Conditions
Horizontal part is internally fed by synchro proces-
sor with a digital signal. corresponding to horizontal
synchro pulses or to TTL composite input.
Concerning the duty cycle of the input signal, the
following signals (positive or negative) may be
applied to the circuit.
Using internal integration, both signals are recog-
nized on condition that Z/T < 25%. Synchronization
occurs on the leading edge of the internal sync
signal. The minimum value of Z is 0.7µs.
Figure 6
An other integration is able to extract vertical pulse
of composite synchroif duty cycle is more than 25%
(typically d = 35%).
Figure 7
C
d
d
TRAMEXT
The last feature performed is the equalizing pulses
removingto avoidparasitic pulseson phasecompara-
tor input which is intolerent to wrong or missing pulse.
II.2 - PLL1
The PLL1 is composed of a phase comparator, an
externalfilter and a voltagecontrolledoscillator (VCO).
The phase comparator is a “phase frequency”type
designed in CMOS technology. This kind of phase
detector avoids locking on false frequencies. It is
followed by a “charge pump”, composed of two
current sources sunk and sourced (I = 1mA Typ.
when locked, I = 140µA when unlocked). This
difference between lock/unlock permits a smooth
catching of horizontal frequency by PLL1. This
effectis reinforcedby an internaloriginal slow down
system when PLL1 is locked avoiding Horizontal
too fast frequency change.
The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
charge pump. A “CRC” filter is generally used (see
Figure 8).
PLL1 is internally inhibited during extractedvertical
sync (if any) to avoid taking in account missing
pulses or wrong pulses on phase comparator.The
inhibition results from the opening of a switch lo-
cated between the charge pump and the filter (see
Figure 9). For particular synchro type, MCU can
drive Pin 3 to high level (TTL compatible input) to
inhibit PLL1. It can also be used to avoid PLL1
locking on synchro inputs if a “dangerous”mode is
detected by the MCU.
The VCO uses an externalRC network. It delivers a
linear sawtooth obtainedby chargeand discharge of
the capacitor, by a current proportionnal to the cur-
rentin the resistor. Typicalthresholdsofsawtoothare
1.6Vand 6.4V. Thesetwo levels are accessibleto be
filtered as on Figure 10 to improve jitter.
Figure 8
PLL1F
12
19/30
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